Flash memory devices have undergone rapid development. Flash memory devices can store data for a considerably long time without powering, and have advantages such as high integration level, fast access, easy erasing, and rewriting.
Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit.
As advances in integration level and increases in demand for storage, to further improve the bit density and reduce cost of flash memory devices, 3D NAND flash memory devices have been developed. A 3D memory architecture can address the density limitation in planar memory cells.
As semiconductor technology advances, 3D memory devices, such as 3D NAND memory devices, keep scaling more oxide/nitride (ON) layers to improve the area utilization of wafers. In some existing 3D NAND memory devices, a memory finger includes multiple rows of channel holes arranged in a staggered manner. It is a challenge to increase memory density while providing uniform channel holes deposition and reducing etch loading effect.